White LED Charge Pump with Mono Class D
Audio Amp and Dual LDO
ILED_ = LED_ [4.0]
ILED_ = 0mA
t OFF_BLINK
t = t LED_RU /32
t ON_BLINK
t = t LED_RD /32
t OFF_BLINK
Figure 6. Combining Ramp Function and Blink Timer (Tables 10 and 11)
LDO1 and LDO2
The linear regulators are designed for low dropout and
low quiescent current to maximize battery life. Both
R INT
MAX8821
LDOs are controlled through the I 2 C interface, minimiz-
ing the number of control lines to the MAX8821. Each
LDO has an individual control register (LDO1_CNTL
AUDIO
INPUTS
C IN
C IN
MONO
CLASS D
AUDIO AMP
EARPIECE/
LOUDSPEAKER
and LDO2_CNTL, Tables 13 and 14). The I 2 C interface
controls the output voltages, and the enable/disable
state for both LDO1 and LDO2.
Thermal Shutdown
The MAX8821 includes a thermal-limit circuit that shuts
down the IC at a junction temperature of approximately
+160°C. The IC turns on after it cools by approximately
20°C.
Shutdown Mode
The MAX8821 can be put into two different shutdown
modes. The first shutdown mode is achieved by driving
V DD low. In this mode, the I 2 C interface becomes dis-
abled. The second shutdown is a lower power mode.
To enter the low-power mode, disable LED_, audio
amplifier, and LDOs through I 2 C. In lower power mode,
the I 2 C interface is still active.
I 2 C Interface
The I 2 C serial interface consists of a serial-data line
(SDA) and a serial-clock line (SCL). Standard I 2 C write-
byte commands are used. Figure 8 shows a timing dia-
gram for the I 2 C protocol. The MAX8821 is a slave-only
device, relying upon a master to generate a clock sig-
nal. The master (typically a microprocessor) initiates
data transfer on the bus and generates SCL to permit
data transfer. A master device communicates to the
MAX8821 by transmitting the proper 8-bit address fol-
lowed by the 8-bit control byte. Each transmit
sequence is framed by a START (A) condition and a
STOP (L) condition. Each word transmitted over the bus
R INT
Figure 7. Optional Input Capacitors
is 8 bits long and is always followed by an acknowl-
edge clock pulse (K).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (A) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (L) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission. One data bit is transferred during
each clock pulse. The data on SDA must remain stable
while SCL is high.
Register Reset
The I 2 C register is reset back to the default value when
either V IN_ drops below the UVLO threshold or V DD is
driven low.
I 2 C Registers and Control
I 2 C Address
The MAX8821 acts as a slave transmitter/receiver. The
slave address of the MAX8821 is preset to 1001110X,
where “X” is the R/W bit. The address 0x9C is designat-
ed for write operations and 0x9D for read operations.
Use Table 1 as a register map to reference the control
bits found in Tables 2–16.
______________________________________________________________________________________
19
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